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14–14
Chapter 14: AltLab Library
DSP Builder supports the SignalTap ? II embedded logic analyzer, which lets you
capture signal activity from internal Altera device nodes while the system under test
runs at speed. Use the SignalTap II Logic Analyzer block to set up event triggers,
configure memory, and display captured waveforms.
You use the SignalTap II Node block to select signals to monitor. Samples are saved to
internal embedded system blocks (ESBs) when the logic analyzer is triggered, and are
subsequently streamed off chip via the JTAG port with an Altera download cable. The
captured data is then stored in a text file, displayed as a waveform in a MATLAB plot,
and transferred to the MATLAB workspace as a global variable.
Table 14–17 shows the SignalTap II Logic Analyzer block parameters.
Table 14–17. SignalTap II Logic Analyzer Block Parameters Page
Name
Scan JTAG
Acquire
SignalTap Nodes
Change
Value
List of ports connected
to the JTAG cable.
—
List of SignalTap II node
blocks.
Don’t Care, High, Low,
Rising Edge, Falling
Edge, Either Edge
Description
The JTAG cable port.
Click to acquire data from the development board.
Click to select a node and use the Change button to set a trigger condition.
Click the Change button to set the specified logic condition as the trigger
condition for the selected node.
f For detailed instructions on with the SignalTap II Logic Analyzer and
SignalTap II Node blocks, refer to the Performing SignalTap II Logic Analysis chapter in
the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder
Handbook .
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
November 2013 Altera Corporation
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